Semiconductor integrated circuit devices typically include a bulk region doped to a first conductivity type (e.g., p-type) that includes “wells” doped to another conductivity type (e.g., n-type). For integrated circuits composed only of logic circuits, such wells can be maintained at essentially a same bias potential. For example, a p-type “bulk” region can be maintained at a low power supply voltage VSS (which is typically ground), while n-wells formed within the bulk can be maintained at a high power supply voltage VDD.
However, for integrated circuits including other types of functions, additional power supply voltages can be received, or a power supply level can vary according to operation. As but one example, integrated circuits containing nonvolatile programmable elements can receive input voltages higher than (or lower than) a normal supply voltage range. Such high voltages can be used for programming and/or erasing such programmable elements. Such circuits can include well bias generator circuits.
One purpose of a well bias generator circuit can be to ensure that the source/bulk connection of p-type field effect transistors (PFETs) in the programming circuitry or in a non-volatile core are not forwarded biased. In some conventional arrangements, well bias generators can include a switch connected a pin of the integrated circuit, because such a pin is “shared”, as it is used as a “normal input” in non-programming operations, or as programming pin in programming operations. This can help reduce a pin count on a device and to allow such a device to be in-package programmable. Since, during non-programming operations, normal inputs can be at a standard power supply voltage, the switch ensures that in a programming operation, the wells are at the highest possible voltage (an applied programming voltage).
To better understand various aspects of the disclosed embodiments, two conventional high voltage switching arrangements will now be described.
A first type of conventional high voltage switch arrangement can use a single well bias switch that follows the higher of a programming voltage input (GPIO) and an input/output power supply voltage (VDDIO). An example of such a conventional approach is shown in FIGS. 8A to 8C, and designated by the general reference character 800. Conventional arrangement 800 is typically used in integrated circuit devices in which the I/O power supply (VDDIO) is physically tied to a core supply (VDDCORE).
A conventional arrangement 800 can include I/O circuitry 802, core circuitry 804, and a well switching circuit 806. I/O circuitry 802 can be considered to have “split” I/O well arrangement, as it can include PFETs having two different well biasing schemes. A first type of PFET (one shown as PIOHV) can receive a supply voltage VDDIO and can be formed in a well biased to the same supply voltage VDDIO. A second type PFET (one shown as PIOLV) can receive another supply voltage VDDCORE, and have a well biased to a bias voltage VWB, where VWB varies according to operation.
Core circuitry 804 can include PFETs biased in the same fashion as transistors PIOLV within I/O circuitry 802.
A well switching circuit 806 can include a PFET structure P80, a first resistance R80 and a second resistance R82. PFET structure P80 can have a source connected to receive voltage GPIO and a drain and body connected to provide bias voltage VWB. A gate of PFET structure P80 can be connected to supply voltage VDDCORE by resistance R80, and to its drain/body by resistance R82.
FIG. 8A shows the operation of conventional switch arrangement 800 under conditions in which GPIO <=VDDCORE, and VDDIO=VDDCORE. Such conditions can occur during “normal” operations. As shown in the figure, if GPIO <=VDDCORE, a source-gate voltage (across resistance R80) is not sufficient to turn on PFET structure P80, consequently, a well bias voltage VWB follows VDDCORE via resistances R80/R82, and as shown by the bold line path.
FIG. 8B shows the operation of conventional switch arrangement 800 under conditions in which GPIO>VDDCORE. Such conditions can occur during “split voltage” operations. Under these conditions, a voltage GPIO is sufficiently large enough to turn on PFET structure P80 (place it into a low impedance state), which can cause well bias voltage VWB to follow GPIO. This biasing path is also shown by a bold line. It is noted that in such an arrangement, well bias voltage VWB can be greater than VDDCORE. Consequently, PFETs in core circuitry 804 and those biased like PIOLV, can have increased threshold voltages (Vts) (as compared to when their respective wells are biased to VDDCORE).
FIG. 8C shows the operation of a conventional switch arrangement 800 under conditions in which GPIO>>VDDCORE. In particular, GPIO is sufficiently large enough that a leakage current (shown as l(leak)) can be created between GPIO and VDDCORE.
A conventional arrangement like that of FIGS. 8A to 8C can have disadvantageously large leakage current, and can require that the various different power supply levels be applied only in a certain order (supply sequencing). This can add to the complexity of any design incorporating such conventional devices. In addition, such approaches impose limits on supply voltage ranges (“headroom”), as increases in the Vts of PFETs resulting from variations in well bias levels have to be accounted for.
Another conventional high voltage switch design architecture is shown in FIGS. 9A and 9B and designated by the general reference character 900. A conventional arrangement 900 can include similar structures to those of FIGS. 8A to 8C, but differs in that I/O circuitry 902 does not include a split well arrangement, having PFETs formed in wells biased to VWB. Within core circuitry 904, PFETs share the same well biasing as I/O circuitry 902, but can receive a lower power supply voltage VDDCORE (which is less than VDDIO). Arrangement 900 further differs from that of FIGS. 8A to 8C, in that a PFET structure P90 can have a gate connected to an I/O supply voltage VDDIO by a resistance R90, and to its drain/body by resistance R92.
FIGS. 9A and 9B show an arrangement in which a well bias switch can follow the higher of an input voltage GPIO or an I/O power supply voltage VDDIO.
FIG. 9A shows the operation of conventional switch arrangement 900 under conditions in which GPIO<=VDDIO. Such conditions can occur during “normal” operations. As shown in the figure, if GPIO <=VDDIO, a source-gate voltage (across resistance R90) is not sufficient to turn on PFET structure P90. Consequently, a well bias voltage VWB follows VDDIO via resistances R90/R92 (shown by the bold line path).
FIG. 9B shows the operation of a conventional switch arrangement 900 under conditions in which GPIO>VDDIO. Under these conditions, a voltage GPIO is sufficiently large enough to turn on PFET structure P90, which can provide a low impedance source-drain path and cause VWB to follow GPIO. This biasing path is also shown by a bold line. As in the case of FIGS. 8A to 8C, such an increase in well bias for devices in core circuitry can result in greater Vts and the resulting drawbacks.
A disadvantage of the second conventional solution of FIGS. 9A and 9B can be that similar problems exist to those of the first conventional solution of FIGS. 8A to 8C, including loss of headroom, the need for supply sequencing, etc.
It is noted that in conventional cases shown above, voltages VDDCORE and VDDIO core are not always maintained at one level, and can be switched during programming to the programming voltage level (often referred to as VPP). Further, during normal operation these voltages may be at levels other than the local supply level.
Disadvantages of the first conventional solution of FIGS. 8A to 8C can include that a well bias voltage VWB follows the higher of VDDIO and GPIO. On devices with a separate core supply or a regulated core, the core supply voltage can be significantly lower than the I/O supply voltage, or it can ramp at a later time than the I/O voltages. As noted above, this can result in a negative source/bulk potential on PFETs in core circuitry. A negative source/bulk potential can raise the Vts of these PFETs. This is an undesirable result since headroom can be lost on sensitive circuits. As but one example, conventional circuits can include power-on-reset (POR) circuits for detecting a power on or reset condition. Such circuits can be based on a “native” Vt of a FET device. As a result, in a conventional arrangement, a POR circuit of a device can trip prior to having enough supply voltage to sufficiently turn on PFETs having changed Vts due to higher well bias levels. This can makes operations like loading non-volatile memories on POR events dependent on the trip voltage supply level or impose a power supply sequencing order.
In addition, as noted above, in a conventional case like that of FIGS. 8A to 8C, a leakage path can exists from the GPIO input to the well especially if a GPIO voltage is sufficiently higher then VDDCORE. This situation can occur, as but one example, for a device having a 3.3V I/O supply (VDDIO) and a 1.8V core supply (VDDCORE) with GPIO at 3.3V. Furthermore, under such conditions, the source/bulk potential of the core devices are now dependent on the GPIO level.